Tech Shout!

IBM Corp. is all set to bring out a 65-nm Power6 server chip running at 5GHz in mid-2007. IBM said the processor is intended for use in financial and high-performance computing like airplane design and automotive crash simulation. The Power6 will double the frequency and bandwidth of the existing Power5 without increasing its power consumption or the depth of its execution pipeline.

The company’s chief engineer for Power6 Brad McCredie said, when the company ships the chip sometime in the middle of 2007, it will target users who are having servers with two to 64 processors.

McCredie said CPU performance cannot be scaled up by just packing more cores and not scaling the cache and memory bandwidth. “What is required is the whole system to be scaled up.”

IBM had set the pattern when it introduced Power4, which has two cores on a single die. It continued this pattern in Power5 and Power6 too will see this pattern being followed.

McCredie said the new chip will use a highly complex latch and static gate circuits. It is built in a 65-nm process using IBM’s silicon-on-insulator (SOI) and strained silicon technology.

The Power CPU will also be linked to an external embedded controller, which will monitor and adjust power and performance parameters on the CPU based on set power management policies.

McCredie said in order to make an impact in high-performance computing field, IBM will have to compete with chips like Sun’s SPARC processors and Intel’s Montecito Itanium 2 processors.